This invention relates to the field of computer aided design of very large scale integration (VLSI) semiconductor circuits and more particularly to the design and production of customizing masks for universal arrays.
Universal array integrated circuits (ICs) are used to test IC designs and for production of ICs. One such universal array is the 800 gate automated universal array or AUA developed by RCA Corporation in cooperation with the Department of the Army under a series of contracts. That AUA is an array of uncommitted devices suitable for conversion into a custom IC by a single patterned customizing conductive layer which can be designed automatically by a computer aided design system from a specification of the IC in terms of logic gates and their interconnections. A plurality of these AUAs are fabricated on a semiconductor wafer. Each AUA comprises an interior row region containing many parallel rows of identical basic units each containing four semiconductor devices. This interior row region is surrounded by a rectangular annular region of peripheral device and contact pads for the connection of external wires to the IC. The rows of basic units are spaced apart by wiring roadbeds. These roadbeds contain wiring channels which run parallel to the length of the rows and wiring lanes which run perpendicular to the length of the rows. Each wiring lane comprises an aligned series of five tunnels which have their adjacent ends spaced apart. All of the tunnels adjacent to one edge of a row comprise a tunnel rank. The next adjacent set of tunnels comprise another tunnel rank and so on. Each tunnel rank has three of the wiring channels disposed thereover.
An electrically insulating layer covers both the semiconductor devices and the tunnels except at predetermined contact points where it is desired to have electrical contact between a semiconductor device or a tunnel and an overlying, conductive, metallic customizing layer. The customizing layer covers an entire major surface of the semiconductor wafer and is initially in electrical contact with the contacts of all the semiconductor devices and tunnels. To customize this universal array semiconductor wafer into a plurality of integrated circuits having a desired set of electrical characteristics, the customizing conductive layer is coated with photoresist and exposed to activating radiation through a custom patterned mask. The custom mask pattern causes the activating radiation to protect those portions of the conductive material which are needed to interconnect the semiconductor devices and tunnels into the desired IC, while leaving unprotected the remaining portions of the customizing conductive layer. The unprotected portions of the customizing layer are removed by etching and the wafer is passivated to prevent environmental damage to the ICs. The completed wafer is tested and diced to provide a plurality of individual ICs all having the desired characteristics.
Where a tunnel in one tunnel rank is to be connected to a tunnel in the next tunnel rank, it can be connected to the aligned tunnel in that next rank or to either of the tunnels adjacent to that aligned tunnel.
The use of a single conductive layer to convert a stock, pre-processed, AUA wafer into a plurality of the desired custom ICs enables rapid completion of the desired ICs once the customizing mask is completed. It is possible to convert a stockpiled wafer into custom ICs in 24 to 48 hours.
Because hand design of a customizing mask for this array is prohibitively time consuming and expensive, an AUA automatic placement and routing system developed by RCA Corporation is used to automatically design the customizing mask. This system, like the array was developed in cooperation with the Department of the Army under a series of contracts. The software for this system is available in source code form from the Army's Electronics Research and Development Command (ERADCOM), Fort Monmouth, N.J. for use on government contracts. That software is known as the AUA or 800 gate AUA program, version 1.5 and is incorporated herein by reference. This computer aided design (CAD) system can produce a customizing mask for this AUA from a specification of the desired IC in terms of logic gates or "logic cells" selected from a set of available "logic cells" and the connections needed between those "logic cells". The term "logic cell" refers to the one or more basic units which when interconnected by customizing conductors form a logic gate such as an AND gate; OR gate, Flip Flop, etc. This CAD system accepts such a specification of the IC and generates a specification of a mask pattern which can be used to pattern the customizing conductive layer to convert a stock 800 gate AUA into the desired custom ICs. This is done through a process involving automatic assignment of logic cells to rows of the universal array, automatic placement of assigned logic cells along the rows and automatic routing of customizing conductors. The resulting mask specification is used to control a mask generating system which converts that specification into the physical pattern of the mask. Thereafter that mask is used in a photoetcher to customize a universal array wafer into a number of the specified ICs.
The computer aided design system must ensure that 100% of the customizing conductors are routed in order for its mask specification to be directly convertible the final mask used to pattern the customizing layer.
Semiconductor area is wasted if a routing system must restrict an IC design to actually using (connecting into its circuit) only a relatively low percentage (such as 60% or 70%) of the universal array's basic units. Some placement and routing systems must impose such restrictions in order to ensure the routing system's ability to complete the routing of 100% of the connecting conductors. It is desirable that the automatic system be able to complete 100% of the routing in circuits which use high percentages (&gt;80%) of the gates which are available in the universal array.
The AUA automatic placement and routing program cited above is capable of routing 100% of the wires in the 800 gate AUA to which it applies, even when as many as 90% or more of the basic units are utiltized in a random logic circuit.
That AUA automatic placement and routing software employs a routing grid in which each point on the grid is defined by a pair of x and y coordinates. The x-axis extends parallel to the length of the rows and the y-axis extends perpendicular to the length of the rows. These routing grid points correspond to physical locations on an actual AUA chip. The grid points are spaced apart in accordance with the design rules of the chip as to conductor width and spacing. Each electrical contact between the customizing layer and a logic cell pin or tunnel contact is located at a grid point. In addition, each location where a conductor may run can be defined in terms of grid points.
The placement part of this AUA software arrives at a final logic cell placement in two phases. In the first phase it tentatively assigns logic cells to individual rows in the row region and then improves that overall assignment through a series of passes through a logic cell exchange routine interleaved with a row length equalization routine.
The cell exchange routine tests whether exchanging a given logic cell on one row with another given logic cell on a different row improves the cell assignment in accordance with its quality criteria. When the logic cells it is proposed to exchange perform different logic functions, they can include significantly different numbers of basic units and therefore can have substantially different lengths. A set of placement quality criteria are evaluated to determine whether a given exchange is an improvement. If the exchange improves the quality of the logic cell placement in accordance with those criteria, then the proposed pair exchange is accepted, otherwise it is rejected. There are several quality criteria. The first is the number of skipped rows for all of the nodes connected to pins of a cell which it is proposed to exchange. A node is a set of pins of active basic units all of which must be connected together by conductors and those connecting conductors. All of the conductors and pins of a node are at the same electrical potential. A skipped row is a row which is crossed by at least one conductor in a node but which contains no cell which has a pin which is part of that node. The second quality criterion is the sum of the number of rows spanned by all of the nodes which connect to the logic cells it is proposed to exchange. The number of rows spanned by a node is also referred to as the y-span of the node. Where the rows are numbered sequentially from bottom to top, the y-span of a node is the number of the uppermost row on which that node has a pin minus the number of the lowermost row on which it has a pin. It is desired to minimize both the number of skipped rows in a node and the y-span of the node. Reducing the number of skipped rows is given a higher priority than reducing the y-span. The third quality citerion is a preference for reducing the length of the longest row in terms of the number of basic units in it which are connected into the circuitry of the IC. Shortening the longest row is given a lower priority than reducing the y-span of the nodes connected to a logic cell.
Most of the proposed cell exchanges turn out to be disadvantageous, a few are advantageous and some are indeterminate because the quality criteria have the same value for both the original and proposed cell assignments. Each time the pair exchange routine is invoked, it is executed repetitively until it no longer provides improvement. During the cell exchange process, there is a limit as to how much longer a row can become than the longest row at the beginning of that execution of the pair exchange routine. This limit is made tighter for each successive invocation of the pair exchange routine. During the final two invocations of the pair exchange routine, the limit is zero. The row length equalization routine is invoked after the completion of each pair exchange routine except for the last two invocations of the pair exchange routine. The row length equalization routine moves logic cells from long rows to short rows to make the length of all rows equal.
Once a final assignment of logic cells to rows has been achieved, this AUA software proceeds to the second phase of its logic cell assignment process. In this second phase the placement software moves logic cells within the row to which they are assigned in accordance with that phase's own quality criteria.
Because of the need for universal arrays with several thousand gates, automatic cell placement software is needed which places logic cells in such a large universal array in a manner which improves the ability of associated automatic routing software to achieve 100% routing of customizing conductors for high gate utilization, complex logic designs.